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Description: 华为公司内部资料，硬件工程师必读的，尤其对刚毕业没有任何开发经验的人，它可以带你登堂入室，给你一个良好的开发习惯。-Huawei internal information, hardware engineers required reading, especially right after graduation without any experience in the development, it can take you tap, you develop a good habit.
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Size: 785408 |
Author: 李钺 |
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Description: 基于FPGA的can 总线设计，采用verilog语言编写。在FPGA的开发环境下，新建一个工程，然后将本文件中的各个源代码添加进工程里，即可运行仿真。-FPGA-based bus design can use verilog language. FPGA development environment, a new project, and then the paper all the source code to add the project, Simulation can be run.
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Size: 862208 |
Author: 李浩 |
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Description: 7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
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Size: 82944 |
Author: lkiwood |
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Description: 一个项目工程，硬件包含XINLINX FPGA，配置FLASH，串口，SDRAM,与以太网芯片DM9000A，实现数据采集，以太网传输，电路验证完全正确，请放心使用，SPARTAN 3E 的BGA引脚320个，不容易布板，可以参考使用的。要FPGA实现网络通信也可以参考电路，B因为产品升级了所以公开原来的电路的。 -A project engineering, hardware contains XINLINX FPGA, configuration FLASH, serial port, SDRAM, and Ethernet chips DM9000A, data acquisition, Ethernet transmission, circuit verification is completely correct, please rest assured that the use of, SPARTAN 3E' s 320-pin BGA it is not easy layout, you can reference to use. To achieve network communication FPGA also can refer to the circuit, because the product upgrades so publicly.
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Size: 915456 |
Author: rong |
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Description: FPGA设计流程，使用者要求有一定的FPGA基础，可以在这个文档的基础上了解更多的FPGA设计方法-FPGA design flow, the user requires a certain degree of FPGA-based, you can on the basis of this document to learn more about FPGA design methodology. . . . . .
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Size: 352256 |
Author: 洪依 |
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Description: 高楼电梯自动控制系统(Windows平台上运行的ispLEVER编程软件。
):
1统控制的电梯往返于1-9层楼。
2客要去的楼层数可手动输入并显示（设为A数）。
3梯运行的楼层数可自动显示（设为B数）。
4A>B时，系统能输出使三相电机正转的时序信号，使电梯上升；
当A<B时，系统能输出使三相电机反转的时序信号，使电梯下降；
当A=B时，系统能输出使三相电机停机的信号，使电梯停止运行并开门；
5是上升还是下降各层电梯门外应有指示，各层电梯门外应有使电梯上升或下降到乘客所在楼层的控制开关。
注：此为word文档，但里面有源代码。-High-rise elevator control system (Windows platform programming software running on the ispLEVER.
):
An elevator control system and from 1-9 floors.
2, the number of passengers going to the floor can manually enter and display (Make A number).
3 ladder run automatically display the number of floors (Set B number).
4A> B, the system can output three-phase motor is transferred to the timing signal to lift up
When A <B, the system can output three-phase motor to reverse the timing signal to the lift down
When A = B, the system can output a signal to shut down three-phase motor, so that the lift stops and open the door
5 is increasing or decreasing the lift on each floor outside the door should be directed, due to lift on each floor outside the elevator up or down to the floor where the passenger control switch.
Note: This is a word document, but inside the source code.
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Size: 34816 |
Author: |
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Description: 设计FPGA电路以模拟多功能电子表的工作过程，功能如下：（1 ）数字钟，要求从00：00 ：00点计到23 ：59：59 （2）数字跑表（3 ）调整时间 (4)闹钟设置，可以设置2个闹钟，闹钟时间到了后会提醒，提醒时间持续20 秒，如果此时按A键，则该闹钟解除提醒，如果按住B键，闹钟暂停提醒。但是3 分钟后重复提醒一次。如果闹钟响时没有按键，则响完20秒之后暂停，然后同样3 分钟后重新提醒一次。（5 ）日期设置。可以设置当前的日期，
比如2012年08月20 日。-Design FPGA circuits to analog the multifunctional electronic table work process, the following functions: (1) digital clock count: 00 points from 00:00 to 23: 59:59 (2) digital the stopwatch (3) to adjust the time (4 ) set the alarm clock, can set two alarm clock, alarm time to remind reminder time for 20 seconds, then press the A key, the alarm clock lifted reminder, if you hold down the B button, snooze alert. But three minutes later repeated reminder. If the alarm goes off, no buttons, sound finished 20 seconds after the pause, and then the same three minutes after the re-remind once. (5) The date is set. Can be set to the current date, such as the August 20, 2012.
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Size: 1664000 |
Author: 章梓音 |
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Description: CAN总线控制器的FPGA源代码，verilog语言编写，支持CAN2.0B协议。对CAN总线开发者非常有用。-FPGA CAN bus controller source code, verilog language, support CAN2.0 protocol B. Developers of CAN bus is very useful.
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Size: 1719296 |
Author: 新一 |
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Description: 交通灯控制器控制两个主干道交叉路口的交通，路口车辆多，直行信号、左转弯信号分开显示，a，b两个主干道的通行时间相等，其中指示直行的绿灯亮30 s，指示左转弯的绿灯亮12 s，绿灯变至红灯时，黄灯亮3 s，以便于车辆能停在停车线内，红灯信号的最后3 s相应的黄灯也同时亮，以便提示驾驶人员准备起步。在两个主干道路口都配备传感器用来检测有无车辆通行。当两个主干道都有车辆时，自动处于主干道a绿灯，主干道b红灯的状态，然后轮流切换通行。当主干道a无车辆时，自动处于主干道b绿灯，主干道a红灯的状态；反之亦然，以提高通行效率。-Traffic light controller controls the two main roads traffic intersection, crossing vehicles, straight signal, left turn signal shown separately, the transit time a, b is equal to two main roads, which indicates straight green light 30 s, indicates that the left turn the green light 12 s, when the green light changed to red light, yellow light 3 s, so that the vehicle can be parked in the parking line, the last 3 s corresponding yellow red signal light also, in order to prompt the driver ready to start . In the two main road junctions are equipped with sensors for detecting the presence or absence of vehicular traffic. When two roads have vehicle automatically in a green trunk, trunk b red state, then turn switch traffic. When the main road without a car, in the trunk b automatic green light, a red light state roads and vice versa, in order to improve traffic efficiency.
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Size: 2205696 |
Author: 江楠 |
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Description: a、设计可显示横彩条和纵彩条的VGA彩条信号；
b、设计可显示英语字母的VGA彩条信号；
c、设计可显示移动彩色斑点的VGA彩条信号；
d、设计可实现手动切换a、b、c三个功能.(The design can display VGA color color and color of the longitudinal cross signal.
The design can display the VGA color signal of the English alphabet.
The design can display the VGA color signal of mobile color spots.)
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Size: 435200 |
Author: ciuciuciu
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Description: This repository includes a pure Vitis HLS implementation of matrix-matrix multiplication (A*B=C) for Xilinx FPGAs, using Xilinx Vitis to instantiate memory and PCIe controllers and interface with the host.
Experiments run on a VCU1525 achieved 462 GFLOP/s, 301 GFLOP/s and 132 GFLOP/s for half, single, and double precision, respectively, with routing across the three SLRs being the primary bottleneck preventing further scaling. The code is not device-specific, and can be configured for any Xilinx FPGA supported by the Xilinx OpenCL runtime. Kernels have also been verified to execute on TUL KU115, Alveo U250, and Alveo U280 boards with similar results.
The implementation uses a systolic array approach, where linearly connected processing elements compute distinct contributions to the outer product of tiles of the output matrix.
The approach used to implement this kernel was presented at FPGA'20 [1]. For a general description of the optimization techniques that we apply, we refer to our article on HLS transformations [2]. We also gave a tutorial on HLS for HPC at SC'21, ISC'21, SC'20, HiPEAC'20, SC'19, SC'18, and PPoPP'18.
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Size: 585044 |
Author: 1679556379@qq.com |
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